The present technology relates to an interface control circuit, a memory system, and a method of controlling the interface control circuit. Specifically, the present technology relates to an interface control circuit, a memory system, and a method of controlling the interface control circuit for detecting and correcting errors in data.
Up until now, memories have been used to retain data in information processing systems. The memories may be classified into non-volatile memories and volatile memories. NAND type flash memories and NOR type flash memories have been widely used as non-volatile memories. In addition, DRAMs (Dynamic Random Access Memories), SRAMs (Static Random Access Memories), or the like have been used as volatile memories.
It has been indicated in recent years that NAND type flash memories and DRAMs among these memories have a limitation in their miniaturization, and thus next-generation memories have been positively proposed and developed as alternatives to existing memories. Examples of the next-generation memories include ReRAMs (Resistive RAMs), PCRAMs (Phase-Change RAMs), and MRAMs (Magnet Resistive RAMs).
One of the characteristics of next-generation non-volatile memories is that they have a higher access speed than those of known NAND type flash memories and NOR type flash memories. In order to suit the high speed performance, the next-generation memories desirably use a high-speed interface such as a DDR (Double-Data-Rate) interface used in DRAMs or the like. JEDEC (Joint Electron Device Engineering Council) as a standards body has also proposed and discussed new standards for applying high-speed interfaces to non-volatile memories. Specifically, a LPDDR (Low-Power Double Data rate) 2-NVM (Non-Volatile Memory) and a LPDDR4-NVM have been, for example, proposed as new standards.
Under these new standards, it is desirable to adjust the phase of a transfer clock and impedance with an interface. This is because, when a phase and impedance are made different from their reference value due to fluctuations in manufacturing process, operation temperature, or the like, there is a high likelihood of a transfer error occurring when data is transferred via the interface. For example, under the standard of a DDR3 interface widely used in DRAMs, a ZQCAL command is prepared to adjust the impedance of the interface (see, for example, “JEDEC STANDARD DDR3 SDRAM Specification JESD79-3B”). Under this standard, a memory system desirably adjusts impedance using a ZQCAL long command immediately after the initialization of a memory. In addition, a memory system is recommended to adjust impedance at regular intervals using a ZQCAL long command and a ZQCAL short command after the initialization of a memory.